CS302 Midterm Online Quiz

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CS302-Midterm

1 / 50

A BCD to 7-Segment decoder has

2 / 50

In ABEL the variable „A‟ is treated separately from variable „a‟

3 / 50

Following is standard POS expression

4 / 50

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________.

5 / 50

  The Quad Multiplexer has _____ outputs

6 / 50

GALcan be reprogrammed because instead of fuses __________logic is used in it

7 / 50

All the ABEL equations must end with ________

8 / 50

Half-Adder Logic circuit contains 2 XOR Gates

9 / 50

A Demultiplexer is not available commercially.

10 / 50

If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________

11 / 50

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

12 / 50

The binary value of 1010 is converted to the product term

13 / 50

The binary value of 1010 is converted to the product term

14 / 50

Circuits having a bubble at their outputs are considered to have an active-low output.

15 / 50

The GAL22V10 has ____ inputs

16 / 50

For a 3-to-8 decoder how many 2-to-4 decoders will be required?

17 / 50

Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer

18 / 50

Demultiplexer has

19 / 50

A latch has _____ stable states

20 / 50

3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.

21 / 50

If“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:

22 / 50

A SOP expression is equal to 1 ______________

23 / 50

The values that exceed the specified range can not be correctly represented and are considered as ________

24 / 50

The ABEL symbol for “OR” operation is

25 / 50

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

26 / 50

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

27 / 50

 The _______ Encoder is used as a keypad encoder.

28 / 50

The Unsigned Binary representation can only represent positive binary numbers

29 / 50

The binary value “1010110” is equivalent to decimal __________

30 / 50

The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code

31 / 50

 The expression _________ is an example of Commutative Law for Multiplication.

32 / 50

An S-R latch can be implemented by using _________ gates

33 / 50

 The maximum number that can be represented using unsigned octal system is _______

34 / 50

In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits

35 / 50

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________.

36 / 50

The output of an AND gate is one when _______

37 / 50

High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________

38 / 50

In the binary number “10011” the weight of the most significant digit is ____

39 / 50

The Quad Multiplexer has _____ outputs 

40 / 50

 A particular Full Adder has  

41 / 50

A logic circuit with an output  consists of ________.

42 / 50

A SOP expression having a domain of 3 variables will have a truth table having ____combinations of inputs and corresponding output values.

43 / 50

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

44 / 50

Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.

45 / 50

The Quad Multiplexer has _____ outputs

46 / 50

 Demultiplexer has

47 / 50

  "Sum-of-Weights" method is used __________

48 / 50

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

49 / 50

Two 2-input, 4-bit multiplexers 74X157 can be connected to implement a ____ multiplexer.

50 / 50

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

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