CS302 Midterm Online Quiz

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CS302-Midterm

1 / 50

If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________

2 / 50

If“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:

3 / 50

If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________

4 / 50

In the Karnaugh map shown above, which of the loops shown represents a legal grouping?

5 / 50

 Tri-State Buffer is basically a/an _________ gate.

6 / 50

 The _______ Encoder is used as a keypad encoder.

7 / 50

NOR gate is formed by connecting _________

8 / 50

Circuits having a bubble at their outputs are considered to have an active-low output.

9 / 50

A latch retains the state unless

10 / 50

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

11 / 50

Tri-State Buffer is basically a/an _________ gate.

12 / 50

The Quad Multiplexer has _____ outputs 

13 / 50

The ABEL symbol for “XOR” operation is

14 / 50

TTL based devices work with a dc supply of ____ Volts

15 / 50

In the binary number “10011” the weight of the most significant digit is ____

16 / 50

Generally, the Power dissipation of devices remains constant throughout their operation.

17 / 50

The 4-variable Karnaugh Map (K-Map) has ______cells for min or max terms

18 / 50

A.(B+ C) = A.B + A.C is the expression of

19 / 50

 The expression _________ is an example of Commutative Law for Multiplication.

20 / 50

 How many data select lines are required for selecting eight inputs?

21 / 50

The binary value of 1010 is converted to the product term

22 / 50

In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits

23 / 50

3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions

24 / 50

The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

25 / 50

 Demultiplexer has

26 / 50

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________.

27 / 50

All the ABEL equations must end with ________

28 / 50

  The Quad Multiplexer has _____ outputs

29 / 50

 The function to be performed by the processor is selected by set of inputs known as ________

30 / 50

The GAL22V10 has ____ inputs

31 / 50

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

32 / 50

The Quad Multiplexer has _____ outputs

33 / 50

The ecimal “8” is represented as using Gray-Code.

34 / 50

The 4-bit 2‟s complement representation of “-7” is _____________

35 / 50

The Unsigned Binary representation can only represent positive binary numbers

36 / 50

A SOP expression is equal to 1 ______________

37 / 50

The ecimal “8” is represented as using Gray-Code.

38 / 50

3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.

39 / 50

The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.

40 / 50

Caveman number system is Base _5 number system

41 / 50

(A+B).(A+C) =  

42 / 50

The binary value of 1010 is converted to the product term

43 / 50

Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer

44 / 50

The diagram given below represents __________

45 / 50

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

46 / 50

The GAL22V10 has ____ inputs

47 / 50

Sequential circuits have storage elements

48 / 50

If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________

49 / 50

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

50 / 50

High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________

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