CS302-Midterm
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The function to be performed by the processor is selected by set of inputs known as ________
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Half-Adder Logic circuit contains 2 XOR Gates
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The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
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A BCD to 7-Segment decoder has
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Two 2-bit comparator circuits can be connected to form single 4-bit comparator
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Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.
7 / 50
The diagram given below represents __________
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The main use of the Multiplexer is to
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Generally, the Power dissipation of _______ devices remains constant throughout their operation.
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A particular Full Adder has
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For a 3-to-8 decoder how many 2-to-4 decoders will be required?
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The binary value of 1010 is converted to the product term
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The binary value “1010110” is equivalent to decimal __________
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Demultiplexer has
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Following is standard POS expression
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The AND Gate performs a logical __________function
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In the binary number “10011” the weight of the most significant digit is ____
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TTL based devices work with a dc supply of ____ Volts
19 / 50
Circuits having a bubble at their outputs are considered to have an active-low output.
20 / 50
The maximum number that can be represented using unsigned octal system is _______
21 / 50
"Sum-of-Weights" method is used __________
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The device shown here is most likely a
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The Quad Multiplexer has _____ outputs
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25 / 50
The range of Excess-8 code is from ______ to ______
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27 / 50
The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
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If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________
29 / 50
The ABEL notation equivalent to Boolean expression A+B is:
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The expression _________ is an example of Commutative Law for Multiplication.
31 / 50
In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits
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Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
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An S-R latch can be implemented by using _________ gates
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The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
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The 4-bit 2‟s complement representation of “-7” is _____________
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The 4-bit 2’s complement representation of “+5” is _____________
38 / 50
In the Karnaugh map shown above, which of the loops shown represents a legal grouping?
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The binary value “11011” is equivalent to __________
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The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.
42 / 50
High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________
43 / 50
Generally, the Power dissipation of devices remains constant throughout their operation.
44 / 50
The OLMC of the GAL16V8 is _______ to the OLMC of the GAL22V10
45 / 50
The function to be performed by the processor is selected by set of inputs known as ____
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48 / 50
The output A < B is set to 1 when the input combinations is __________
49 / 50
A standard POS form has __________ terms that have all the variables in the domain of the expression.
50 / 50
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