CS302 Midterm Online Quiz

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CS302-Midterm

1 / 50

The main use of the Multiplexer is to

2 / 50

The diagram given below represents __________

3 / 50

 The function to be performed by the processor is selected by set of inputs known as ________

4 / 50

A Karnaugh map is similar to a truth table because it presents all the possible values of inputvariables and the resulting output of each value.

5 / 50

The AND Gate performs a logical __________function

6 / 50

 A particular Full Adder has  

7 / 50

In the binary number “10011” the weight of the most significant digit is ____

8 / 50

"Sum-of-Weights" method is used __________ 

9 / 50

A SOP expression having a domain of 3 variables will have a truth table having ____combinations of inputs and corresponding output values.

10 / 50

  The Quad Multiplexer has _____ outputs

11 / 50

Which one is true:

12 / 50

A standard POS form has __________ terms that have all the variables in the domain of the expression.

13 / 50

3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.

14 / 50

 The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

15 / 50

  The Quad Multiplexer has _____ outputs

16 / 50

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

17 / 50

The output A < B is set to 1 when the input combinations is

18 / 50

The device shown here is most likely a

19 / 50

A latch has _____ stable states

20 / 50

The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.

21 / 50

For a 3-to-8 decoder how many 2-to-4 decoders will be required?

22 / 50

A BCD to 7-Segment decoder has

23 / 50

In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits

24 / 50

Following is standard POS expression

25 / 50

 The binary value “11011” is equivalent to __________

26 / 50

If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________

27 / 50

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

28 / 50

  "Sum-of-Weights" method is used __________

29 / 50

The binary value of 1010 is converted to the product term

30 / 50

The binary value “1010110” is equivalent to decimal __________

31 / 50

The values that exceed the specified range can not be correctly represented and are considered as ________

32 / 50

A logic circuit with an output  consists of ________.

33 / 50

The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code

34 / 50

Two 2-bit comparator circuits can be connected to form single 4-bit comparator

35 / 50

The OLMC of the GAL16V8 is _______ to the OLMC of the GAL22V10

36 / 50

The output of an AND gate is one when _______

37 / 50

Half-Adder Logic circuit contains 2 XOR Gates

38 / 50

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

39 / 50

In the Karnaugh map shown above, which of the loops shown represents a legal grouping?

40 / 50

The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

41 / 50

NOR Gate can be used to perform the operation of AND, OR and NOT Gate

42 / 50

Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer

43 / 50

The range of Excess-8 code is from ______ to ______

44 / 50

NOR gate is formed by connecting _________

45 / 50

GAL is an acronym for ________.

46 / 50

The Quad Multiplexer has _____ outputs 

47 / 50

The range of Excess-8 code is from ______ to ______

48 / 50

A.(B.C) = (A.B).C is an expression of __________

49 / 50

In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits

50 / 50

The binary value of 1010 is converted to the product term

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