CS501 Midterm Online Quiz

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CS501-Midterm

1 / 50

FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC _____wide.

2 / 50

Identify the opcode, destination register (DR), source registers (SA and SB i/e source register A and source register B) from the following example. ADD R1, R2, R3

3 / 50

Almost every commercial computer has its own particular ---------- language

4 / 50

In which one of the following techniques, the time a processor spends waiting for instructions to be fetched from memory is minimized? Select correct option:

5 / 50

 -------------- performs the data operations as commanded by the program instructions.

6 / 50

What is the instruction length of the SRC processor?

7 / 50

Which operator is used to „name‟ registers, or part of registers, in the Register Transfer Language?

8 / 50

Which of the instruction is used to load register from memory using a relative address?

9 / 50

___________ or Branch instructions affect the order in which instructions are performed, or control the flow of the program

10 / 50

_________control signals enable the input to the PC for receiving a value that is currently on the internal processor bus.

11 / 50

The instruction ___________ will load the register R3 with the contenets of the m\emory location M [PC+56]

12 / 50

Which one of the following is the memory organization of FALCON-E processor?

13 / 50

 “If P = 1, then load the contents of register R1 into register R2”. This statement can be written in RTL as:

14 / 50

Which of the following can be defined as an address of the operand in a computer type instruction or the target address in a branch type instruction?

15 / 50

Which one of the following is a bi-stable device, capable of storing one bit of information?

16 / 50

_____________ controller controls the sequence of the flow of microinstructions.

17 / 50

Which one of the following registers stores a previously calculated value or a value loaded from the main memory?

18 / 50

Motorola MC68000 is an example of ---------microprocessor.

19 / 50

Which one of the following is the code size and the Number of memory bytes respectively for a 2-address instruction?

20 / 50

which type of instructions help in changing the flow of the program as and when required?

21 / 50

Flip-flop is a ____________device, capable of storing one bit of Information

22 / 50

The CPU includes three types of instructions, which have different operands and will need different representations. Which one of the instructions requires two source registers?

23 / 50

For the __________ type instructions, we require a register to hold the data that is to be loaded from the memory, or stored back to the memory

24 / 50

Which one of the following portions of an instruction represents the operation to be performed?

25 / 50

The data movement instructions ___________ data within the machine and to or from input/output devices.

26 / 50

Which field of the machine language instruction is the “type of operation” that is to be performed?

27 / 50

What does the word „D‟ in the „D-flip-Flop‟ stands for?

28 / 50

An “assembler” that runs on one processor and translates an assembly language program written for another processor into the machine language of the other processor is called a ----------------

29 / 50

What functionality is performed by the instruction “lar R3, 36” of SRC?

30 / 50

_________ control signal allows the contents of the Program Counter register to be written onto the internal processor bus.

31 / 50

_____________all memory systems are dumb, in that they respond to only two commands: read or write.

32 / 50

Which one of the following register(s) that is/are programmer invisible and is/are required to hold an operand or result value while the bus is busy transmitting some other value?

33 / 50

For any of the instructions that are a part of the instruction set of the SRC, there are cerain_________required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.

34 / 50

Computer system performance is usually measured by the ---------------

35 / 50

________ operation is required to change the processor‟s state to a known, defined value.

36 / 50

Which one of the following registers holds the address of the next instruction to be executed?

37 / 50

What is the working of Processor Status Word (PSW)?

38 / 50

Type A of SRC has which of the following instructions?

  1. A) andi, instruction
  2. b) No operation or nop instruction
  3. c) lar instruction
  4. d) ldr instruction
  5. e) Stop operation or stop instruction

39 / 50

-----------is the ability of application software to operate on models of equipment newer than the model for which it was originally developed. Select correct option:

40 / 50

___________ or Branch instructions affect the order in which instructions are performed, or control the flow of the program

41 / 50

What is the size of the memory space that is available to FALCON-A processor?

42 / 50

Which one of the following register holds the instruction that is being executed?

43 / 50

Register-register instructions use ____________ memory operands out of a total of 3 operands

44 / 50

_____________all memory systems are dumb, in that they respond to only two commands: read or write

45 / 50

Which one of the following register(s) contain(s) the address of the place the CPU wants to work with in the main memory and is/are directly connected to the RAM chips on the motherboard?

46 / 50

FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC is __________ wide.

47 / 50

The code size of 2-address instruction is ________________.

48 / 50

How can we refer to an instruction register (IR), of 16 bits (numbered 0 to 15) using RTL?

49 / 50

What functionality is performed by the instruction “str R8, 34” of SRC?

50 / 50

Which one of the following registers holds the instruction that is being executed?

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