CS302-Midterm
1 / 50
The output A < B is set to 1 when the input combinations is __________
2 / 50
The ecimal “8” is represented as using Gray-Code.
3 / 50
"Sum-of-Weights" method is used __________
4 / 50
High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________
5 / 50
The output of an AND gate is one when _______
6 / 50
The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
7 / 50
The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.
8 / 50
The function to be performed by the processor is selected by set of inputs known as ____
9 / 50
The main use of the Multiplexer is to
10 / 50
2's complement of any binary number can be calculated by
11 / 50
Following is standard POS expression
12 / 50
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
13 / 50
The AND Gate performs a logical __________function
14 / 50
Sequential circuits have storage elements
15 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
16 / 50
If“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:
17 / 50
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
18 / 50
NOR gate is formed by connecting _________
19 / 50
An important application of AND Gate is its use in counter circuit
20 / 50
The diagram given below represents __________
21 / 50
The maximum number that can be represented using unsigned octal system is _______
22 / 50
The binary value “1010110” is equivalent to decimal __________
23 / 50
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
24 / 50
In the binary number “10011” the weight of the most significant digit is ____
25 / 50
A latch retains the state unless
26 / 50
The Quad Multiplexer has _____ outputs
27 / 50
How many data select lines are required for selecting eight inputs?
28 / 50
In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits
29 / 50
The device shown here is most likely a
30 / 50
GAL is an acronym for ________.
31 / 50
In the Karnaugh map shown above, which of the loops shown represents a legal grouping?
32 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________.
33 / 50
34 / 50
A.(B+ C) = A.B + A.C is the expression of
35 / 50
The _______ Encoder is used as a keypad encoder.
36 / 50
The binary value of 1010 is converted to the product term
37 / 50
The 4-bit 2’s complement representation of “+5” is _____________
38 / 50
39 / 50
Demultiplexer has
40 / 50
Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.
41 / 50
The Unsigned Binary representation can only represent positive binary numbers
42 / 50
A BCD to 7-Segment decoder has
43 / 50
A logic circuit with an output consists of ________.
44 / 50
The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
45 / 50
Generally, the Power dissipation of devices remains constant throughout their operation.
46 / 50
A Demultiplexer is not available commercially.
47 / 50
A particular Full Adder has
48 / 50
A Karnaugh map is similar to a truth table because it presents all the possible values of inputvariables and the resulting output of each value.
49 / 50
Tri-State Buffer is basically a/an _________ gate.
50 / 50
The 4-variable Karnaugh Map (K-Map) has ______cells for min or max terms
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