CS302-Midterm
1 / 50
Generally, the Power dissipation of devices remains constant throughout their operation.
2 / 50
If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________
3 / 50
A.(B+ C) = A.B + A.C is the expression of
4 / 50
A particular Full Adder has
5 / 50
The AND Gate performs a logical __________function
6 / 50
Tri-State Buffer is basically a/an _________ gate.
7 / 50
The output A < B is set to 1 when the input combinations is __________
8 / 50
The output A < B is set to 1 when the input combinations is
9 / 50
If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________
10 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
11 / 50
The Unsigned Binary representation can only represent positive binary numbers
12 / 50
The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
13 / 50
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
14 / 50
Half-Adder Logic circuit contains 2 XOR Gates
15 / 50
Two 2-bit comparator circuits can be connected to form single 4-bit comparator
16 / 50
Circuits having a bubble at their outputs are considered to have an active-low output.
17 / 50
In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits
18 / 50
The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
19 / 50
A logic circuit with an output consists of ________.
20 / 50
The Quad Multiplexer has _____ outputs
21 / 50
Caveman number system is Base _5 number system
22 / 50
The ABEL notation equivalent to Boolean expression A+B is:
23 / 50
A latch has _____ stable states
24 / 50
Which one is true:
25 / 50
An S-R latch can be implemented by using _________ gates
26 / 50
27 / 50
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
28 / 50
High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________
29 / 50
An important application of AND Gate is its use in counter circuit
30 / 50
Demultiplexer has
31 / 50
Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
32 / 50
GALcan be reprogrammed because instead of fuses __________logic is used in it
33 / 50
A standard POS form has __________ terms that have all the variables in the domain of the expression.
34 / 50
(A+B).(A+C) =
35 / 50
For a 3-to-8 decoder how many 2-to-4 decoders will be required?
36 / 50
The ecimal “8” is represented as using Gray-Code.
37 / 50
Generally, the Power dissipation of _______ devices remains constant throughout their operation.
38 / 50
39 / 50
40 / 50
The 4-bit 2‟s complement representation of “-7” is _____________
41 / 50
42 / 50
3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.
43 / 50
The expression _________ is an example of Commutative Law for Multiplication.
44 / 50
45 / 50
GAL is an acronym for ________.
46 / 50
The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.
47 / 50
The diagram given below represents __________
48 / 50
How many data select lines are required for selecting eight inputs?
49 / 50
50 / 50
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