CS302-Midterm
1 / 50
Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.
2 / 50
3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.
3 / 50
The binary value of 1010 is converted to the product term
4 / 50
The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
5 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________.
6 / 50
Sequential circuits have storage elements
7 / 50
The ABEL symbol for “XOR” operation is
8 / 50
Two 2-bit comparator circuits can be connected to form single 4-bit comparator
9 / 50
A latch retains the state unless
10 / 50
2's complement of any binary number can be calculated by
11 / 50
GAL is an acronym for ________.
12 / 50
If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________
13 / 50
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
14 / 50
The binary value “1010110” is equivalent to decimal __________
15 / 50
16 / 50
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
17 / 50
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
18 / 50
A SOP expression having a domain of 3 variables will have a truth table having ____combinations of inputs and corresponding output values.
19 / 50
A latch has _____ stable states
20 / 50
The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.
21 / 50
Half-Adder Logic circuit contains 2 XOR Gates
22 / 50
The function to be performed by the processor is selected by set of inputs known as ____
23 / 50
Tri-State Buffer is basically a/an _________ gate.
24 / 50
A standard POS form has __________ terms that have all the variables in the domain of the expression.
25 / 50
High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________
26 / 50
The OR Gate performs a Boolean _______ function
27 / 50
Which one is true:
28 / 50
The _______ Encoder is used as a keypad encoder.
29 / 50
The expression _________ is an example of Commutative Law for Multiplication.
30 / 50
"Sum-of-Weights" method is used __________
31 / 50
The ecimal “8” is represented as using Gray-Code.
32 / 50
The output A < B is set to 1 when the input combinations is
33 / 50
In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits
34 / 50
A.(B.C) = (A.B).C is an expression of __________
35 / 50
In the binary number “10011” the weight of the most significant digit is ____
36 / 50
How many data select lines are required for selecting eight inputs?
37 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
38 / 50
The GAL22V10 has ____ inputs
39 / 50
40 / 50
The maximum number that can be represented using unsigned octal system is _______
41 / 50
42 / 50
Circuits having a bubble at their outputs are considered to have an active-low output.
43 / 50
The range of Excess-8 code is from ______ to ______
44 / 50
The output A < B is set to 1 when the input combinations is __________
45 / 50
(A+B).(A+C) =
46 / 50
The 4-bit 2‟s complement representation of “-7” is _____________
47 / 50
A particular Full Adder has
48 / 50
49 / 50
For a 3-to-8 decoder how many 2-to-4 decoders will be required?
50 / 50
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