CS302-Midterm
1 / 50
GALcan be reprogrammed because instead of fuses __________logic is used in it
2 / 50
The range of Excess-8 code is from ______ to ______
3 / 50
The binary value “1010110” is equivalent to decimal __________
4 / 50
The ecimal “8” is represented as using Gray-Code.
5 / 50
NOR gate is formed by connecting _________
6 / 50
Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
7 / 50
The 4-variable Karnaugh Map (K-Map) has ______cells for min or max terms
8 / 50
Half-Adder Logic circuit contains 2 XOR Gates
9 / 50
The values that exceed the specified range can not be correctly represented and are considered as ________
10 / 50
Caveman number system is Base _5 number system
11 / 50
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
12 / 50
If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________
13 / 50
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
14 / 50
The GAL22V10 has ____ inputs
15 / 50
TTL based devices work with a dc supply of ____ Volts
16 / 50
17 / 50
Two 2-bit comparator circuits can be connected to form single 4-bit comparator
18 / 50
The ABEL symbol for “OR” operation is
19 / 50
A particular Full Adder has
20 / 50
The function to be performed by the processor is selected by set of inputs known as ________
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If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
22 / 50
Generally, the Power dissipation of devices remains constant throughout their operation.
23 / 50
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
24 / 50
A latch retains the state unless
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26 / 50
An S-R latch can be implemented by using _________ gates
27 / 50
Demultiplexer has
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The output A < B is set to 1 when the input combinations is
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30 / 50
The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.
31 / 50
Following is standard POS expression
32 / 50
In the binary number “10011” the weight of the most significant digit is ____
33 / 50
The Quad Multiplexer has _____ outputs
34 / 50
The Unsigned Binary representation can only represent positive binary numbers
35 / 50
Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.
36 / 50
2's complement of any binary number can be calculated by
37 / 50
Tri-State Buffer is basically a/an _________ gate.
38 / 50
The 4-bit 2’s complement representation of “+5” is _____________
39 / 50
The OR Gate performs a Boolean _______ function
40 / 50
GAL is an acronym for ________.
41 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________.
42 / 50
43 / 50
The output A < B is set to 1 when the input combinations is __________
44 / 50
If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________
45 / 50
A BCD to 7-Segment decoder has
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48 / 50
A.(B.C) = (A.B).C is an expression of __________
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50 / 50
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