CS302-Midterm
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The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.
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The ABEL symbol for “XOR” operation is
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GAL is an acronym for ________.
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The GAL22V10 has ____ inputs
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The maximum number that can be represented using unsigned octal system is _______
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For a 3-to-8 decoder how many 2-to-4 decoders will be required?
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If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
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Two 2-bit comparator circuits can be connected to form single 4-bit comparator
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Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.
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The PROMconsists of a fixed non-programmable ____________ Gate array configured as a decoder.
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TTL based devices work with a dc supply of ____ Volts
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If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________
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Tri-State Buffer is basically a/an _________ gate.
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The expression _________ is an example of Commutative Law for Multiplication.
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The Quad Multiplexer has _____ outputs
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The AND Gate performs a logical __________function
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If“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:
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A latch has _____ stable states
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"Sum-of-Weights" method is used __________
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A BCD to 7-Segment decoder has
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The OLMC of the GAL16V8 is _______ to the OLMC of the GAL22V10
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The main use of the Multiplexer is to
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A SOP expression having a domain of 3 variables will have a truth table having ____combinations of inputs and corresponding output values.
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If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________
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Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
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The device shown here is most likely a
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If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________.
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The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
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(A+B).(A+C) =
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In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits
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The range of Excess-8 code is from ______ to ______
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The ecimal “8” is represented as using Gray-Code.
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The binary value “11011” is equivalent to __________
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The binary value “1010110” is equivalent to decimal __________
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The Unsigned Binary representation can only represent positive binary numbers
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The output of an AND gate is one when _______
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The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
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Which one is true:
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A standard POS form has __________ terms that have all the variables in the domain of the expression.
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Sequential circuits have storage elements
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A particular Full Adder has
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The function to be performed by the processor is selected by set of inputs known as ____
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An S-R latch can be implemented by using _________ gates
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Half-Adder Logic circuit contains 2 XOR Gates
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Caveman number system is Base _5 number system
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The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
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