CS302-Midterm
1 / 50
The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
2 / 50
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
3 / 50
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
4 / 50
The diagram given below represents __________
5 / 50
The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
6 / 50
Two 2-input, 4-bit multiplexers 74X157 can be connected to implement a ____ multiplexer.
7 / 50
8 / 50
Demultiplexer has
9 / 50
High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________
10 / 50
If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________
11 / 50
12 / 50
A particular Full Adder has
13 / 50
The function to be performed by the processor is selected by set of inputs known as ________
14 / 50
The OR Gate performs a Boolean _______ function
15 / 50
An important application of AND Gate is its use in counter circuit
16 / 50
The output A < B is set to 1 when the input combinations is __________
17 / 50
The AND Gate performs a logical __________function
18 / 50
Half-Adder Logic circuit contains 2 XOR Gates
19 / 50
Which one is true:
20 / 50
21 / 50
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
22 / 50
An S-R latch can be implemented by using _________ gates
23 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
24 / 50
For a 3-to-8 decoder how many 2-to-4 decoders will be required?
25 / 50
The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ hererepresents OR Gate.
26 / 50
2's complement of any binary number can be calculated by
27 / 50
NOR gate is formed by connecting _________
28 / 50
A logic circuit with an output consists of ________.
29 / 50
Two 2-bit comparator circuits can be connected to form single 4-bit comparator
30 / 50
31 / 50
32 / 50
The GAL22V10 has ____ inputs
33 / 50
Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.
34 / 50
"Sum-of-Weights" method is used __________
35 / 50
If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________
36 / 50
Following is standard POS expression
37 / 50
GALcan be reprogrammed because instead of fuses __________logic is used in it
38 / 50
The PROMconsists of a fixed non-programmable ____________ Gate array configured as a decoder.
39 / 50
A latch has _____ stable states
40 / 50
A standard POS form has __________ terms that have all the variables in the domain of the expression.
41 / 50
Tri-State Buffer is basically a/an _________ gate.
42 / 50
The output of an AND gate is one when _______
43 / 50
In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits
44 / 50
The 4-bit 2‟s complement representation of “-7” is _____________
45 / 50
The Quad Multiplexer has _____ outputs
46 / 50
The binary value of 1010 is converted to the product term
47 / 50
48 / 50
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
49 / 50
The function to be performed by the processor is selected by set of inputs known as ____
50 / 50
The binary value “1010110” is equivalent to decimal __________
Your score is
The average score is 44%
Restart quiz
