CS302-Midterm
1 / 50
In the Karnaugh map shown above, which of the loops shown represents a legal grouping?
2 / 50
A particular Full Adder has
3 / 50
Generally, the Power dissipation of _______ devices remains constant throughout their operation.
4 / 50
The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
5 / 50
The binary value of 1010 is converted to the product term
6 / 50
The diagram given below represents __________
7 / 50
Caveman number system is Base _5 number system
8 / 50
The output A < B is set to 1 when the input combinations is __________
9 / 50
A Demultiplexer is not available commercially.
10 / 50
The Quad Multiplexer has _____ outputs
11 / 50
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
12 / 50
The expression _________ is an example of Commutative Law for Multiplication.
13 / 50
Two 2-input, 4-bit multiplexers 74X157 can be connected to implement a ____ multiplexer.
14 / 50
Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS 5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal (VoH) will be in the range of _______ volts.
15 / 50
In ABEL the variable „A‟ is treated separately from variable „a‟
16 / 50
The range of Excess-8 code is from ______ to ______
17 / 50
The values that exceed the specified range can not be correctly represented and are considered as ________
18 / 50
A.(B.C) = (A.B).C is an expression of __________
19 / 50
Circuits having a bubble at their outputs are considered to have an active-low output.
20 / 50
Demultiplexer has
21 / 50
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
22 / 50
Which one is true:
23 / 50
If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________
24 / 50
NOR gate is formed by connecting _________
25 / 50
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
26 / 50
Half-Adder Logic circuit contains 2 XOR Gates
27 / 50
A BCD to 7-Segment decoder has
28 / 50
2's complement of any binary number can be calculated by
29 / 50
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
30 / 50
Tri-State Buffer is basically a/an _________ gate.
31 / 50
The ABEL notation equivalent to Boolean expression A+B is:
32 / 50
The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
33 / 50
Two 2-bit comparator circuits can be connected to form single 4-bit comparator
34 / 50
A SOP expression is equal to 1 ______________
35 / 50
The AND Gate performs a logical __________function
36 / 50
The ABEL symbol for “OR” operation is
37 / 50
The ecimal “8” is represented as using Gray-Code.
38 / 50
39 / 50
In ANSI/IEEE Standard 754 “Mantissa” is represented by 32-bits bits
40 / 50
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
41 / 50
For a 3-to-8 decoder how many 2-to-4 decoders will be required?
42 / 50
GAL is an acronym for ________.
43 / 50
3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.
44 / 50
The output A < B is set to 1 when the input combinations is
45 / 50
46 / 50
The binary value “1010110” is equivalent to decimal __________
47 / 50
48 / 50
Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
49 / 50
Sequential circuits have storage elements
50 / 50
Generally, the Power dissipation of devices remains constant throughout their operation.
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